1. Field of the Invention
The present invention relates to a thin film transistor array substrate to be used in a liquid crystal display device and the like.
2. Description of the Background Art
Conventionally, major examples of liquid crystal display devices have a structure having a TFT array substrate (hereinafter an “array substrate”) formed with a pixel electrode and a thin film transistor (TFT) for supplying a display signal to the pixel electrode, a counter substrate formed with a common electrode, and a liquid crystal layer held between the TFT array substrate and the counter substrate. The liquid crystal display devices have a TN (Twisted Nematic) mode for driving liquid crystal through an electric field of a vertical direction (direction vertical to a surface of the array substrate and the counter electrode) generated between the pixel electrode and the common electrode, and a VA (Vertical Alignment) mode. Further, in recent years, liquid crystal display devices which employ an IPS (In-Plane Switching) mode (“IPS” is a registered trademark) and an FFS (Fringe Field Switching) mode have been put to practical use. In these modes, both a pixel electrode and a common electrode are disposed on an array substrate and liquid crystal is driven by an electric field of a lateral direction generated between the pixel electrode and the common electrode.
Japanese Patent Application Laid-Open No. 2009-128397, for example, proposes a structure where in a liquid crystal display panel of the FFS mode, a thick insulating film (flattening film) is formed on a source wiring (display signal line) and a portion above the source wiring is covered with a common electrode. With this structure, a source wiring type common electrode shields an electric field from a pixel, and simultaneously reduces a parasitic capacitance between the pixel and the source wirings so as to be capable of reducing power consumption of the liquid crystal panel.
In the liquid crystal display panel of the FFS mode, the pixel electrode and the common electrode are formed on different layers. For this reason, a dry etching process needs to be executed at least twice in order to form a first aperture (contact hole) for connecting a common electrode to a wiring (common wiring) for supplying a potential to the common electrode, and a second aperture for connecting a pixel electrode to a drain electrode of TFT for supplying a display signal to the pixel electrode.
Further, when a flattening film on the drain electrode of TFT is removed at the step of forming the first aperture before the step of forming the second aperture, the surface of the drain electrode is damaged twice by dry etching for forming the first aperture and dry etching for forming the second aperture. This occasionally causes an increase in contact resistance between the pixel electrode and the drain electrode. On the other hand, when the first aperture and the second aperture are formed simultaneously, one more aperture should be formed in order to connect the common electrode to the common wiring, and thus an area ratio of the contact hole within a pixel region increases.
Further, when a flattening film (organic flattening film) whose material is organic resin is used, the organic flattening film remains on a region other than the apertures of terminal portions. For this reason, a new countermeasure against the reduction in adhesion of packaging is necessary.